Telecommunications equipment hardware for transmission and switching of packetized data are typically realized by interconnections of various integrated circuits. One or more of these integrated circuit devices are used to implement the functions of a layer in the communications protocol stack. The physical layer and link layer functions are typically implemented in separate devices that communicate with each other over a common interface. Such an interface must be designed to enable reliable and efficient data transfer. Various interfaces have been developed over the past few years to meet requirements of particular applications at the time. Recently, some interface proposals have been made to address requirements of packet and ATM cell transfer at data rates of up to 10 Gb/s (OC-192 SONET/SDH and 10 Gb/s Ethernet). The first is “UTOPIA Level 4” af-phy-0144.001, ATM Forum (ref. 1) and the second is “Proposal for a Common System Physical Interface Level 4 (SPI-4) to Support Physical Line Rates of up to 10 Gbps” (also known as SPI-4 Phase 1) Oif99.127, Optical Internetworking Forum (ref. 2).
The following definitions will be useful in the discussions to follow. The transmit data path refers to the signals associated with data transfer from the Link Layer to the physical layer (PHY) device. Conversely, the receive data path refers to transfer from the PHY device to the Link Layer device.
In ref. 1, control and status signals are sent together with payload data (i.e., sent “in-band”) in a 32-bit wide data path. As shown in FIG. 1, there are separate transmit and receive data paths. Data (tx_data[31:0], rx_data[31:0]), control (tx_ctrl, rx_ctrl), and clock (tx_clk, rx_clk) lines are all implemented using LVDS I/O, operating at a nominal frequency of 400 MHz. Control and status for transmit data transfer is sent in the receive data path. Likewise, control and status for receive data transfer is sent in the transmit data path. When a control line is high in any given cycle, the corresponding data lines contain control information. Conversely, when a control line is low, the data lines contain payload data. The format of the control information is shown in FIG. 2.
In ref. 2, control and status signals are sent on separate lines (i.e., sent “out-of-band”) from the 64-bit data path as shown in FIG. 3. All signals are implemented with HSTL Class 1 I/O, operating at a nominal frequency of 200 MHz. Flow control is accomplished by indicating FIFO full/not full status in a round-robin manner as shown in FIG. 4. When high, TxStart and RxStart indicate the start of a round-robin sequence. Other signal definitions are summarized as follows. TxClk and RxClk are the clock lines. TxAddr[n:1] and RxAddr[n:1] indicate the port associated with the data transfer. TxData[63:0] and RxData[63:0] are used to carry payload data. TxPrty[3:03] and RxPrty[3:0] are parity bits calculated over the TxData and RxData lines. TxSOCP and RXSOCP indicate the start of a cell or packet. TxEOP and RxEOP indicate the cycle containing an end of packet. TxSize[3:0]) and RxSize[3:0] indicate which bytes of a 64-bit word are valid upon end of packet. TxValid and RxValid indicate when the corresponding data lines are valid. TxError and RxError are used to indicate the occurrence of an error condition upon end of packet.
In principle, both ref. 1 and ref. 2 could be used for data transfer in 10 Gb/s applications. However, they suffer from various limitations. Both schemes have very high pin counts (136 and 164 pins for ref. 1 and ref. 2, respectively), which together with pins required for other functions, require larger IC package sizes. Moreover, their high pin counts inherently limit the number of interfaces that can be included in a given device, compared to a lower pin count interface. Both ref. 1 and ref. 2 also consume a relatively high amount of power (estimated at 4.08 and 3.42 W respectively, not including power consumption at the receivers). Both schemes specify only binary (i.e., full/not full) FIFO status information; more detailed FIFO status information could be used by the scheduler at the far end to arrange data transfers to various ports so as to optimize transfer efficiency and to better avoid FIFO overflow and underflow conditions.
Since FIFO status information is sent in-band with data in ref. 1, it is difficult to use such an interface with unidirectional devices on either end (e.g., separate transmit and receive devices on either the PHY or the Link Layer side of the interface). An example for the case of unidirectional link layer devices is shown in FIG. 5, where an interface between those devices is required for sending FIFO status. For example, flow control information from the PHY for the transmit Link Layer device would be received by a Receive Link Layer device, which would then send the information onto the Transmit Link Layer device to complete the feedback loop. Flow control information from the Receive Link Layer device itself would also need to be sent to the Transmit Link Layer device for in-band transmission to the PHY device. This additional interface between the Transmit and Receive Link Layer devices requires not only additional pins (along with attendant additional power consumption), but will also require additional engineering effort to specify and validate.
The control signaling protocol in ref. 1 permits arbitrary insertion of control words at any point during data transfer. Such a protocol is needlessly complicated for the requirements at hand and is difficult to verify. Moreover, since several control words can elapse between one that contains parity information, the control signal (tx_ctrl/rx_ctrl) itself must also be included in the parity calculation if it is also to be protected, It is much simpler to have control words inserted only between data transfers, and to have parity contained in each control word.
With ref. 2, the parity bits protect only the data lines. It would be beneficial to have error protection over not only the data but also the associated control and status lines.
Accordingly, it is an object of the present invention to provide data recovery in the presence of skew between parallel data lines. It is a further object to provide a system interface for packet and cell transfer for OC-192 SONET/SDH and 10 Gb/s Ethernet Applications that have a lower pin count. It is yet another object of the invention to provide such an interface which has a lower power consumption. Another object of the invention is to provide such an interface having a simplified operation with minimal overhead, and better signal integrity. Finally, it is a further object of the invention to provide a system interface which is suitable for unidirectional link layer device implementations with error protection on data and control signals and 3-state flow control indication.